1. Field
This embodiment relates to an A/D (Analog/Digital) converter, which may convert analog signals input from a plurality of channels.
2. Description of the Related Art
An A/D converter is known which selects desired channels from a plurality of channels of analog inputs, and performs A/D conversion.
In the case where the A/D converter of this kind is provided with a single register for storing results of A/D conversion, it is required, whenever an analog signal input from a channel is A/D-converted, to generate an interrupt for requesting an external control circuit (CPU (Central Processing Unit) or the like) to read the result of A/D conversion. This results in frequent generation of the interrupt and lowered throughput of the external control circuit. Further, when the A/D converter is provided with registers for all the channels, respectively, the circuit scale of the A/D converter increases, and since all the channels are not necessarily used, some of the provided registers sometimes are not necessary.
In view of this, an A/D converter has been proposed which is provided with a smaller number of registers than the number of channels thereof, and has the channels thereof divided into several groups (hereinafter referred to as “the channel groups”), whereby a read-requesting interrupt is caused to be generated whenever A/D conversion of each channel group is completed. For example, Japanese Laid-Open Patent Publication (Kokai) No. H09-269870 discloses an A/D converter in which input channels are switched not by an external CPU but by an internal sequencer, thereby making it possible to shorten a time period taken to switch the channel groups.
In the conventional A/D converter, however, the interrupt is generated when the conversion of each channel group is completed, and hence when transfer of the result of A/D conversion to the outside is not performed in time, the register can be overwritten with the result of A/D conversion of the next channel group.
Further, when e.g. a change in information on a specific channel is desired to be inspected, A/D conversion of the same channel is repeated. In this case, in the conventional A/D converter, the registers for storing the results of A/D conversion are fixed on a channel-by-channel basis. Therefore, when the A/D conversion of the same channel is repeated, the results of the preceding A/D conversion are overwritten by the results of the following A/D conversion. Therefore, it is required to generate an interrupt to a control circuit, such as a CPU, to cause the same to read information in the register whenever A/D conversion is completed. This increases load on the control circuit, and results in an increased processing time period.